Flash memory cell and method for manufacturing the same

ABSTRACT

An active region and a trench region are formed on a semiconductor substrate. The trench region is filled with a dielectric material to form an isolation layer. Oxide and polysilicon layers are formed on the semiconductor substrate. A second polysilicon layer, a second oxide layer, and a first polysilicon layer are patterned to form a plurality of gate lines. Deep ion implantation in a deep portion of the active region is performed using a self-aligned source mask. The active region and the trench region are exposed through the self-aligned source mask by etching the isolation layer between the plurality of gate lines using the self-aligned source mask to form a common source region. Ions are implanted in the common source region using the self-aligned source mask.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application No.10-2004-0111472, filed on Dec. 23, 2004, which is hereby incorporated byreference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a flash memory cell and a method formanufacturing the same.

2. Discussion of the Related Art

A flash memory cell is a device fabricated by adopting the merits andprinciples of EPROM, which has programmable and erasablecharacteristics, and of EEPROM which has electrically programmable anderasable characteristics. The flash memory cell includes a thin tunneloxide film formed on a silicon substrate, a floating gate and a controlgate stacked on the oxide film, and source and drain regions formed onan exposed portion of the substrate. A dielectric layer is interposedbetween the floating gate and the control gate. The flash memory cellallows storage of one bit in a single transistor and performs electricalprogramming and erasing.

The flash memory cell includes a source connecting layer which connectssource regions of respective unit cells to form a source line. Thesource connecting layer can be fabricated by a metal contact methodwhich connects metal contacts to one another after forming the metalcontacts in the respective unit cells. However, this method is notsuitable for highly integrated devices due to contact margin.Accordingly, a common source line comprising an impurity diffusion layerformed by a self-aligned source (SAS) process has been increasinglyapplied so that high integration of devices may be implemented.

Specifically, with a multilayered gate electrode formed on a substrate,the SAS process exposes a source region of each cell by using a separateSAS mask. A field oxide film is then removed by anisotropic etching toform a common source line adjacent cells. The SAS process can reduce thearea of each cell in a bit line direction, especially a space betweenthe gate and the source region. Thus, it is a necessary process for a0.25 μm level technique. The SAS. process described above can reduce thearea of the cell by about 20%. However, the SAS process has at least onedisadvantage. When the SAS process is applied in a memory cell where thecommon source line is formed along a profile of a trench region, acontact resistance of the source region in each cell is rapidlyincreased in practice. The resistance of the common source line isincreased because as a junction resistance is generated along a featureof the trench region, the length of an actual sheet resistance and aspecific resistance of a sidewall in the trench region are increased.Ion implantation is performed such that a relatively small dose of ionsis implanted to the sidewall of the trench region. Thus, the resistanceof the sidewall is considerably increased.

For most memory cells having a level of 0.25 μm to 0.18 μm or less, ashallow-trench isolation process is used as an isolation technique. Theshallow-trench isolation process and the SAS process are necessaryprocesses that reduce the area of the cells in a word line direction andin a bit line direction, respectively. However, when both processes aresimultaneously applied, a problem occurs in that a source resistance isremarkably increased.

Since the flash memory cell employs an internal high voltage, the depthof the trench region is increased corresponding to the reduction in thearea of the cell. Thus, the length of the common source line graduallyincreases, thereby providing a disadvantageous effect to the sourceresistance. For an embedded flash memory cell, detrimental effectsoccur, such as deterioration in programming characteristics and readspeed.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a flash memory celland a method for manufacturing the same that substantially obviates oneor more of the problems due to limitations and disadvantages of therelated art.

The present invention can provide a flash memory cell and a method formanufacturing the same that minimizes contact resistance in a commonsource line when applying a SAS process.

Additional features and advantages of the invention will be set forth inthe description which follows, and in part will be apparent from thedescription, or may be learned from practice of the invention. Theobjectives and other advantages of the invention will be realized andattained by the structure and method particularly pointed out in thewritten description and claims hereof as well as the appended drawings.

To achieve these and other advantages and in accordance with the purposeof the present invention, as embodied and broadly described, a flashmemory cell comprises a semiconductor substrate having an active regionand a trench region; a first oxide layer, a first polysilicon layer, asecond oxide layer, and a second polysilicon layer formed on thesemiconductor substrate; a plurality of trench lines formed parallel toeach other; a plurality of gate lines formed perpendicular to theplurality of trench lines; and a common source region formed parallel toand between the plurality of gate lines by implanting ions into theactive region and the trench region, wherein a depth of ions implantedin the trench region is the same as a depth of ions implanted in theactive region.

In another aspect of the present invention, a method for manufacturing aflash memory cell comprises forming an active region and a trench regionon a semiconductor substrate; filling the trench region with adielectric material to form an isolation layer; forming a first oxidelayer, a first polysilicon layer, a second oxide layer, and a secondpolysilicon layer on the semiconductor substrate; patterning the secondpolysilicon layer, the second oxide layer, and the first polysiliconlayer to form a plurality of gate lines; performing deep ionimplantation in a deep portion of the active region using a self-alignedsource mask; exposing the active region and the trench region throughthe self-aligned source mask by etching the isolation layer between theplurality of gate lines using the self-aligned source mask to form acommon source region; and implanting ions in the common source regionusing the self-aligned source mask.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and areintended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention, illustrate embodiment(s) of theinvention and together with the description serve to explain theprinciples of the invention. In the drawings:

FIG. 1 is a layout view of a flash memory cell according to the presentinvention;

FIG. 2 is a cross-sectional view along line II-II′ of FIG. 1;

FIGS. 3 to 5 are cross-sectional views of a flash memory cellillustrating a method according to the present invention; and

FIG. 6 is a cross-sectional view of a flash memory cell illustrating adeep ion implantation in a method according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to embodiments of the presentinvention, examples of which are illustrated in the accompanyingdrawings. Wherever possible, like reference designations will be usedthroughout the drawings to refer to the same or similar parts. Also,layer thickness, relative proportions, and other dimensions as depictedmay be exaggerated or distorted in the drawings to more clearly depictsemiconductor components and materials, including layers, films, plates,and other areas. Furthermore, description of a component or materialthat, for example, is disposed or formed “directly on” (i.e., abutting)an underlying component or material is an indication that there is nointerceding component or material, while other descriptions, includingbeing “formed on” an underlying component or material, is to be taken asan indication that the described component or material may be disposedmerely “above” (i.e., at any level higher than) the underlying componentor material.

As shown in FIGS. 1 and 2, the flash memory cell according to anembodiment of the present invention includes a plurality of trench lines19 formed parallel to the bit lines (BL) on a semiconductor substrate100. The plurality of trench lines 19 corresponds to an isolationregion. A dotted line indicates a border of an inclined side surface ofthe trench lines 19.

The flash memory cell further includes a common source region 12 formedbeneath the surface of the semiconductor substrate 100. The commonsource region 12 is formed by ion implantation of impurities in adirection of a word line.

A plurality of gate lines 13 is formed perpendicular to the plurality oftrench lines 19, i.e., the plurality of gate lines 13 is parallel to theword line. A drain region 15 is formed in a region opposite the commonsource region 12 with respect to the plurality of gate lines 13. Thedrain region 15 has a drain contact 17 formed at a portion of the drainregion 15.

As shown in FIG. 1, a portion of the plurality of gate lines 13 and agap between adjacent gate lines 13 are exposed through a self-alignedsource (SAS) mask 200. A border of an exposed portion of the SAS mask200 is on the gate lines 13 and aligned with and parallel to theplurality of gate lines 13.

As shown in FIGS. 2 and 5, after the common source region 12 is formedusing the SAS mask, ions 72 are implanted onto a surface of the trenchregion 53 b and ions 61 are implanted into a deep portion of the sourceregion 51. Accordingly, a common source line 20 in the common sourceregion 12 is formed in a substantially straight line along the surfaceof the trench region 53 b and the surface of the source region 51,thereby reducing the resistance of the common source line 20.

FIGS. 3-5 respectively illustrate steps of an exemplary method formanufacturing the flash memory cell according to the present invention.

As shown in FIG. 3, an active region 51 and a trench region 53 areformed on a semiconductor substrate 100. An isolation layer 52 is formedby filling the trench region 53 with a dielectric material. The trenchregion 53 corresponds to the plurality of trench lines 19 of FIG. 1. Theplurality of trench lines 19 is formed parallel to a plurality of bitlines. A first oxide layer is then formed on the semiconductor substrate100 excluding the plurality of trench lines 19. Then, a firstpolysilicon layer, a second oxide layer, and a second polysilicon layerare deposited on the semiconductor substrate 100 and the first oxidelayer. Then, the second polysilicon layer, the second oxide layer, andthe first polysilicon layer are successively etched by aphotolithography process to thereby form a plurality of gate lines 13perpendicular to the plurality of trench lines 19 i.e., the gate lines13 are parallel to the word lines.

Then, deep ion implantation is performed using an SAS mask. This allowsa portion of the plurality of gate lines 13 and a gap between adjacentgate lines 13 to be exposed. Ions are deeply implanted into theisolation layer 52 and the source region 51. For example, ions 61 areimplanted to 70% of a total depth of the isolation layer 52, and ions 62are implanted to a portion in the source region 51 slightly deeper thanthe ions 61 in the isolation layer 52.

The implanted ions 61 and 62 are N-type ions, and may be arsenic (As) orphosphorous (P) ions. For arsenic ions, a dose of N-type ions of5×10¹⁴-5×10¹⁵ and an implantation energy of 300-500 KeV for the N-typeions may be used. For phosphorous ions, a dose of N-type ions of5×10¹⁴-5×10¹⁵ and an implantation energy of 150-300 KeV for the N-typeions may be used.

The deep ion implantation may be performed in an inclined ionimplantation, as shown in FIG. 6. The inclined ion implantation isperformed in parallel with the word line, and half of the ions arepreferably implanted at a positive angle (+β) and the remaining ions areimplanted at a negative angle (−β).

As shown in FIG. 4, the surfaces of the trench region 53 and the sourceregion 51 are exposed by etching the isolation layer 52 formed betweenthe adjacent gate lines 13 in the first oxide layer and the trench lines19 using the SAS mask. Then, the ions 62 implanted to the isolationlayer 52 are removed by removing the isolation layer 52.

Ion implantation is performed as shown in FIG. 5. During this process,ions 70, including ions 71, 72 and 73, are implanted to the surfaces ofthe source region 51 and the trench region 53 along the common sourceregion 12.

Ions 73 are implanted at an angle of α to a sidewall 53 a of the trenchregion 53. Accordingly, a junction depth and a dose of the ions 73 arereduced by sin(α) of the original ion implantation energy and dose. As aresult, the resistance of ions 73 implanted to the sidewall 53 a of thetrench region 53 can be ten-fold or more than that of other portions.

Ions 72 implanted to the surface of the trench region 53 and ions 61implanted to a deep portion of the source region 51 via deep ionimplantation are connected to each other and have a substantiallyidentical height. However, since ions 72 and 61 are implanted in thismanner, ions 71 implanted to the surface of the source region 51 andions implanted to the sidewall 53 a of the trench region 53 are excludedfrom the common source line 20. In addition, the ions 73 implanted tothe sidewall 53 a of the trench region 53 do not substantially providethe effect of increased resistance.

In the flash memory cell and the method for manufacturing the sameaccording to the present invention, deep ion implantation is performedbefore etching the isolation layer 52 such that the common source lineof the common source region is formed in a straight line along thesurfaces of the trench region and the source region, thereby reducingthe resistance of the common source line. As a result, the flash memorycell of the present invention can remarkably reduce the voltage drop(I×R) and has improved reading and programming efficiencies. Thus, theflash memory cell of the present invention has enhanced characteristics.

It will be apparent to those skilled in the art that variousmodifications and variation can be made in the present invention withoutdeparting from the spirit or scope of the invention. Thus, it isintended that the present invention cover the modifications andvariations of this invention provided they come within the scope of theappended claims and their equivalents.

1. A flash memory cell, comprising: a semiconductor substrate having anactive region and a trench region; a first oxide layer, a firstpolysilicon layer, a second oxide layer, and a second polysilicon layerformed on said semiconductor substrate; a plurality of trench linesformed parallel to each other; a plurality of gate lines formedperpendicular to said plurality of trench lines; and a common sourceregion formed parallel to and between said plurality of gate lines byimplanting ions into the active region and the trench region, wherein adepth of ions implanted in the trench region is approximately the sameas a depth of ions implanted in the active region.
 2. The flash memorycell according to claim 1, wherein the active region is a source region.3. The flash memory cell according to claim 1, wherein the plurality oftrench lines is parallel to a bit line and wherein the plurality of gatelines is parallel to a word line. 4-17. (canceled)